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Acquisition of Asynchronous Data in Software Embed Code 39 Extended in Software Acquisition of Asynchronous Data

7. using none torender none for asp.net web,windows application USPS POSTNET Barcode Acquisition of Asynchronous Data 7.1 Motivation Most digital syste none none ms that interact with the external world must handle asynchronous inputs because events outside that system appear at random points in time with respect to the system s internal operation. As an example, a crankshaft angle sensor generates a pulse train regardless of the state of operation of the electronic engine management unit that processes those pulses. Synchronization problems are not con ned to electromechanical interfaces.

Much the same situation occurs when electronic systems interact that are mutually independent, in spite or precisely because of the fact that each of them is operating in a strictly synchronous way. Just think of a workstation that exchanges data with a le server over a local area network (LAN), of audio data that are being brought to a D/A converter for output, or of a data bus that traverses the borderline from one clock domain to another. Obviously, the processing of asynchronous inputs is more frequent in digital systems than one would like.

The following episode can teach us a lot about the di culty of accommodating asynchronously changing input signals. The account is due to the late Charles E. Molnar, who was honest enough to tell us about all misconceptions he and his colleagues went through until the problems of synchronization were fully understood.

. Historical example Back in 1963, a te none for none am of electronics engineers was designing a computer for biological researchers that was to be used for collecting data from laboratory equipment. In order to in uence program execution from that apparatus, a mechanism was included to conditionally skip one instruction depending on the binary status of some external signal. The basic idea behind that design, sketched in g.

7.1a, was to increment the computer s program counter one extra time via a common enable input of its ip- ops i the external signal was at logic 1..

7.1 MOTIVATION from external input putative clock boundary from external input clock boundary synchronization flip-flop +2 program counter program counter computer computer Fig. 7.1 Control u none for none nit with conditional instruction skip mechanism (simpli ed).

Original design without synchronization (a), improved design with external signal synchronized (b).. When monitoring th e computer s operation, the engineering team observed that the next instruction was occasionally being fetched from a bogus address after the external signal had been asserted, thereby causing the computer to lose control over program execution. As an example, either of 0 1111 = 15 or 1 0000 = 16 is expected to follow after address 0 1110 = 14, depending on the external input. Instead, the program counter could be observed to enter a state such as 1 1101 = 29 or 0 0010 = 2.

The team soon found out that such failures developed only if the external signal happened to change just as the active clock edge was about to occur, causing the program counter to end up with a wild mix of old and new bits. The obvious solution was to insert a synchronization ip- op so as to make a single decision as to whether the external level was 0 or 1 at the time of clock. Although the improved design, sketched in g.

7.1b, performed much better than the initial one, the team continued to observe sporadic jumps to unexpected memory locations, a failure pattern for which it had no satisfactory explanation at the time. It took almost a decade before Molnar and others who worked on high-speed interfaces1 dared publicly report on the anomalous behavior of synchronizers and before journals would accept such reports that contrasted with general belief.

Two failure mechanisms are exposed by this case, namely data inconsistency and synchronizer metastability, both of which will be discussed in this chapter together with advice on how to get them under control.. W hat was consider none for none ed high sp eed yesterday, no longer is high sp eed to day. In the context of synchronization, high-sp eed always refers to circuits that op erate at clo ck frequencies and data rates approaching the lim its of the underlying technology..

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